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16 - bit, 1 msps pulsar adc in msop/qfn ad7980 - ep rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any i nfringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and re gistered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2010 analog devices, inc. all rights reserved. features 16- bit resolution with no missing codes throughput: 1 msps low power dissipation: 7.0 mw @ 1 msps, 70 w @ 10 ksps inl: 1.5 lsb typical, 1.25 lsb maximum sinad: 91. 5 db @ 10 khz thd: ?11 4 db @ 10 khz pseudo differential analog input range 0 v to v ref with v ref between 2.5 v to 5.5 v any input range and easy to drive with the ada4841 no pipeline delay single - supply 2.5 v operation with 1.8 v/2.5 v/3 v/5 v logic interface serial interface spi - /qspi? - /microwire? - /dsp - compatible daisy - chain multiple adcs and busy indicator supports defense and aerospace applications (aqec) controlled manufacturing baseline one assembly/test site one fabrication site enhanced product change notification qualification data available on request 10- lead msop military t emperature range: ? 55c to +125c applications battery - powered equipment communications ate data acquisitions medical instruments application diagram example ad7980-e p ref gnd vdd in+ in? vio sdi sck sdo cnv 1.8v t o 5.0v 3- or 4-wire inter f ace (spi, dais y chain, cs) 2.5v t o 5v 2.5v 0 t o vref 09304-001 figure 1. general description the ad7980 - ep is a 16 - bit, successive approximation, anal og - to - digital converter (adc) that operates from a single power supply, vdd. it contains a low power, high speed, 16 - bit sampling adc and a versatile serial interface port. on the cnv rising edge, it samples an analog input in+ between 0 v to ref with resp ect to a ground sense in ?. the reference voltage, ref, is applied externally and can be set independent of the supply voltage, vdd. its power scales linearly with throughput. the spi - compatible serial interface also features the ability, using the sdi inpu t, to daisy - chain several adcs on a single, 3 - wire bus and provides an optional busy indicator. it is compatible with 1.8 v, 2.5 v, 3 v, or 5 v logic, using the separate supply vio. the ad7980 - ep is housed in a 10 - lead msop with operation specified from ? 55c to +125c. table 1 . msop, qfn (lfcsp) 14 - /16- /18 - bit pulsar? adc type 100 ksps 250 ksps 400 ksps to 500 ksps 1000 ksps adc driver 18- bit ad7691 1 ad7690 1 ad7982 1 ada4941 ada4841 16- bit ad7680 ad7685 1 ad7686 1 ad7980 1 ada4941 ad7683 ad7687 1 ad7688 1 ada4841 ad7684 ad7694 ad7693 1 14- bit ad7940 AD7942 1 ad7946 1 1 pin - for - pin compatible.
ad7980- ep rev. 0 | page 2 of 12 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 application diagram example ........................................................ 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications ....................................................................... 5 absolute maximum ratings ............................................................6 esd caution ...................................................................................6 pin configurations and function descriptions ............................7 typical performance characteristics ..............................................8 outline dimensions ....................................................................... 12 ordering guide .......................................................................... 12 revision history 9 /10 revision 0: initial version
ad7980- ep rev. 0 | page 3 of 12 specifications vdd = 2.5 v, vio = 2.3 v to 5.5 v, v ref = 5 v, t a = C 55c to +125c, unless otherwise n oted. table 2 . parameter conditions min typ max unit resolution 16 bits analog input voltage range in+ ? in? 0 v ref v absolute input voltage in+ ? 0.1 v ref + 0.1 v in ? ? 0.1 +0.1 v analog input cmrr f in = 100 khz 60 db leakage current @ 25c acquisition phase 1 na accuracy no missing codes 16 bits differential linearity error ref = 5 v ? 0.9 0.4 +0.9 lsb 1 ref = 2.5 v 0.55 lsb 1 integral linearity er ror ref = 5 v ? 1.5 0.6 +1.5 lsb 1 ref = 2.5 v 0.65 lsb 1 transition noise ref = 5 v 0.6 lsb 1 ref = 2.5 v 1.0 lsb 1 gain error, t min to t max 2 2 lsb 1 gain error temperature drift 0.35 ppm/c zero error, t min to t max 2 ? 0.62 0.08 +0.62 mv zero temperature drift 0.54 ppm/c power supply sensitivity vdd = 2.5 v 5% 0.1 lsb 1 throughput conversion rate vio 2.3 v up to 85c, vio 3.3 v above 85c up to 125c 0 1 msps transient response full - scale step 290 ns ac accuracy dynamic range v ref = 5 v 92 db 3 v ref = 2.5 v 87 db 3 oversampled dynamic range f o = 10 ksps 111 db 3 signal -to - noise ratio, snr f in = 10 khz, v ref = 5 v 91 db 3 f in = 10 khz, v ref = 2.5 v 86.5 db 3 spurious - free dynamic range, sf dr f in = 10 khz ? 110 db 3 total harmonic distortion, thd f in = 10 khz ? 114 db 3 signal - to - (noise + distortion), sinad f in = 10 khz, v ref = 5 v 91.5 db 3 f in = 10 khz, v ref = 2.5 v 87.0 db 3 1 lsb means least significant bit. with the 5 v input range, 1 lsb is 76.3 v. 2 these specifications include full temperature range variation , but not the error contribution from the external reference. 3 all specifications in db are referred to a full - scale input fs r . tested with an input signal at 0.5 db below full scale, unless oth erwise specified.
ad7980- ep rev. 0 | page 4 of 12 vdd = 2.5 v, vio = 2.3 v to 5.5 v, v ref = 5 v, t a = C 55c to +125c, unless otherwise noted. table 3 . parameter conditions min typ max unit reference voltage range 2.4 5.1 v load current 1 msps, ref = 5 v 330 a sampling dynamics ? 3 db input bandwidth 10 mhz aperture delay vdd = 2.5 v 2.0 ns digital inputs logic levels v il vio > 3v C 0.3 0.3 vio v v ih vio > 3v 0.7 vio vio + 0.3 v v il vio 3v C 0.3 0.1 vio v ih vio 3v 0.9 vio vio + 0.3 a i il ? 1 +1 a i ih ? 1 +1 a digital outputs data format serial 16 bits straight binary pipeline delay conversion results available immediately after completed conversion v ol i sink = 500 a 0.4 v v oh i source = ?500 a vio ? 0.3 v power suppl ies vdd 2.375 2.5 2.625 v vio specified performance 2.3 5.5 v vio range 1.8 5.5 v standby current 1 , 2 vdd and vio = 2.5 v, 25c 0.35 na power dissipation 10 ksps throughput 70 w 1 msps throughput 7.0 10 mw energy per conversion 7.0 nj/sample temperature range specified performance t min to t max ? 55 +125 c 1 with all digital inputs forced to vio or gnd as required. 2 during the acquisition phase.
ad7980- ep rev. 0 | page 5 of 12 timing specification s ?55c to +125c, vdd = 2.37 v to 2.63 v, vio = 3.3 v to 5.5 v, unless otherwise stated. see figure 2 and figure 3 for load conditions. t able 4 . parameter symbol min typ max unit conversion time: cnv rising edge to data available t conv 500 710 ns acquisition time t acq 290 ns time between conversions t cyc 1000 ns cnv pulse width ( cs t cnvh mod e) 10 ns sck period ( cs t sck mode) ns vio above 4.5 v 10.5 ns vio above 3 v 12 ns vio above 2.7 v 13 ns vio above 2.3 v 15 ns sck period (chain mode) t sck ns vio above 4.5 v 11.5 ns vio above 3 v 13 ns vio above 2.7 v 14 ns vio above 2.3 v 16 ns sck low time t sckl 4.5 ns sck high time t sckh 4.5 ns sck falling edge to data remains valid t hsdo 3 ns sck falling edge to data valid delay t dsdo vio above 4.5 v 9.5 ns vio abo ve 3 v 11 ns vio above 2.7 v 12 ns vio above 2.3 v 14 ns cnv or sdi low to sdo d15 msb valid ( cs t en mode) vio above 3 v 10 ns vio above 2.3 v 15 ns cnv or sdi high or last sck falling edge to sdo high impeda nce ( cs t dis mode) 20 ns sdi valid setup time from cnv rising edge t ssdicnv 5 ns sdi valid hold time from cnv rising edge ( cs t hsdicnv mode) 2 ns sdi valid hold time from cnv rising edge (chain mode) t hsdicnv 0 ns sck valid setup time from cnv rising edge (chain mode) t ssckcnv 5 ns sck valid hold time from cnv rising edge (chain mode) t hsckcnv 5 ns sdi valid setup time from sck falling edge (chain mode) t ssdisck 2 ns sdi valid hold time from sck falling edge (chain mode) t hsdisck 3 ns sdi high to sdo high (chain mode with busy indicator) t dsdosdi 15 ns 500 a i ol 500 a i oh 1.4v t o sdo c l 20pf 09304-002 figure 2 . load circuit for digital interface timing x% vio 1 y% vio 1 v ih 2 v il 2 v il 2 v ih 2 t delay t delay 1 for vio 3.0v, x = 90 and y = 10; for vio > 3.0v x = 70, and y = 30. 2 minimum v ih and maximum v il used. see digital inputs specifications in table 3. 09304-003 figure 3 . voltage levels for timing
ad7980-ep rev. 0 | page 6 of 12 absolute maximum ratings table 5. parameter rating analog inputs in+, in? to gnd ?0.3 v to v ref + 0.3 v or 130 ma supply voltage ref, vio to gnd ?0.3 v to +6 v vdd to gnd ?0.3 v to +3 v vdd to vio +3 v to ?6 v digital inputs to gnd ?0.3 v to vio + 0.3 v digital outputs to gnd ?0.3 v to vio + 0.3 v storage temperature range ?65c to +150c junction temperature 150c ja thermal impedance (10-lead msop) 200c/w jc thermal impedance (10-lead msop) 44c/w lead temperature vapor phase (60 sec) 215c infrared (15 sec) 220c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad7980- ep rev. 0 | page 7 of 12 pin configurations a nd function descript ions ref 1 vdd 2 in+ 3 in? 4 vio 10 sdi 9 sck 8 sdo 7 gnd 5 cnv 6 ad7980-e p t op view (not to scale) 09304-004 figure 4 . 10 - lead msop pin configuration table 6 . pin function descriptions pin no. mnemonic 1 ref 2 vdd 3 in+ 4 in ? 5 gnd 6 cnv 7 sdo 8 sck 9 sdi 10 vio
ad7980- ep rev. 0 | page 8 of 12 typical performance characteristics vdd = 2 .5 v, v ref = 5.0 v, vio = 3.3 v, unless otherwise noted. 1.25 ?1.25 0 65536 code inl (lsb) 1.00 0.75 0.50 0.25 ?0.25 ?0.75 0 ?0.50 ?1.00 16384 32768 49152 positive inl: +0.33 lsb negative inl: ?0.39 lsb 09304-036 figure 5 . integral nonlinearity vs. code, ref = 5 v 1.25 1.00 ?1.25 ?1.00 0 65536 code inl (lsb) 0.75 0.50 0.25 ?0.25 ?0.75 0 ?0.50 16384 32768 49152 positive inl: +0.47 lsb negative inl: ?0.26 lsb 09304-060 figure 6 . integral nonlinearity vs. code, ref = 2.5 v 0 ?180 0 500 frequency (khz) amplitude (db of full scale) ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 100 200 300 400 f s = 1 msps f in = 10khz snr = 91.27db thd = ?114.63db sfdr = 110.10db sinad = 91.25db 09304-038 figure 7 . fft plot, ref = 5 v 1.00 ?1.00 0 65536 code dnl (lsb) 0.75 0.50 0.25 ?0.25 ?0.75 0 ?0.50 16384 32768 49152 positive inl: +0.18 lsb negative inl: ?0.21 lsb 09304-039 figure 8 . differential nonlinearity vs. code, ref = 5 v 1.00 ?1.00 0 65536 code dnl (lsb) 0.75 0.50 0.25 ?0.25 ?0.75 0 ?0.50 16384 32768 49152 positive inl: +0.25 lsb negative inl: ?0.22 lsb 09304-061 figure 9 . differential nonlinearity vs. code, ref = 2.5 v 0 ?180 0 500 frequency (khz) amplitude (db of full scale) ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 100 200 300 400 f s = 1 msps f in = 10khz snr = 86.8db thd = ?111.4db sfdr = 105.9db sinad = 86.8db 09304-058 figure 10 . fft plot, ref = 2.5 v
ad7980- ep rev. 0 | page 9 of 12 180k 0 800c 800d 800e 800f 8009 8008 800b 800 a 8003 8005 8004 8007 8006 2 0 0 0 33 829 0 27 0 1201 code in hex counts 140k 160k 100k 120k 60k 20k 80k 40k 38751 168591 52710 09304-042 figure 11 . histogram of a dc input at the code center, ref = 5 v 70k 0 7fff 8008 8001 8000 8003 8002 8005 8004 8007 8006 0 0 150 2 59691 5428 59404 3 93 code in hex counts 60k 50k 30k 10k 40k 20k 6295 09304-043 figure 12 . histogram of a dc input at the code transition, ref = 5 v 100 80 85 90 95 2.25 5.25 reference voltage (v) snr, sinad (db) 16 12 13 14 15 enob (bits) 2.75 3.25 3.75 4.25 4.75 snr sinad enob 09304-044 figure 13 . snr, sinad, and enob vs. reference voltage 60k 0 7f f a 8006 7ffc 7ffb 7ffe 7fff 7ffd 8001 8000 8003 8004 8005 8002 0 0 0 0 539 16 14 502 code in hex counts 50k 30k 10k 40k 20k 32417 52212 31340 7225 6807 09304-059 figure 14 . histogram of a dc input at the code center, ref = 2.5 v 95 85 87 89 92 91 93 94 86 88 90 ?10 0 input level (db of full scale) snr (db) ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 09304-046 figure 15 . snr vs. input level ?95 ?125 ?1 10 ?1 15 ?105 ?100 ?120 1 15 85 100 95 105 1 10 90 2.25 5.25 reference voltage (v) thd (db) sfdr (db) 2.75 3.25 3.75 4.25 4.75 thd sfdr 09304-047 figure 16 . thd, sfdr vs. reference voltage
ad7980- ep rev. 0 | page 10 of 12 100 80 10 1000 frequency (khz) sinad (db) 95 90 85 100 09304-063 figure 17 . sinad vs. frequency 95 85 89 87 91 93 ?55 125 temperature (c) snr (db) ?35 ?15 5 25 65 85 45 105 09304-049 figure 18 . snr vs. temperature 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 current (ma) 2.425 2.475 vdd vo lt age (v) 2.375 2.525 2.575 2.625 i vdd i ref i vio 09304-050 figure 19 . operating currents vs. supply ?85 ?125 10 1000 frequency (khz) thd (db) 100 ?90 ?95 ?100 ?105 ?110 ?115 ?120 09304-064 figure 20 . thd vs. frequency ?1 10 ?120 thd (db) ?55 ?35 ?15 5 25 temper a ture (c) 45 65 85 105 125 ?112 ?114 ?116 ?118 09304-052 figure 21 . thd vs. temperature 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 current (ma) ?55 ?35 ?15 5 25 temper a ture (c) 45 65 85 105 125 i vdd i ref i vio 09304-053 figure 22 . operating currents vs. temperature
ad7980- ep rev. 0 | page 11 of 12 8 7 6 5 4 3 2 1 0 current (a) ?55 ?35 ?15 5 25 temper a ture (c) 45 65 85 105 125 i vdd + i vio 09304-054 figure 23 . power - down currents vs. temperature
ad7980-ep rev. 0 | page 12 of 12 outline dimensions compliant to jedec standa rds m o-187-ba 091709-a 6 0 0.70 0.55 0.40 5 10 1 6 0.50 bsc 0.30 0.15 1.10 max 3.10 3.00 2.90 co planar ity 0.10 0.23 0.13 3.10 3.00 2.90 5.15 4 .90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 figure 24 .10 - lead mini small outline package [msop] (rm - 10) dimensions shown in millimeters ordering guide model integral nonlinearity temperature range ordering quantity package description package option branding ad7980srmz -ep - rl7 1 1.5 lsb max ? 55c to +125c reel, 1,000 10- lead msop rm - 10 c78 1 z = rohs compliant part. ? 2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09304 -0- 9/10(0)

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